1. Field of the Invention
The present invention relates to switched mode power supplies, and more particularly to digital control signal processor architecture optimized for controlling a switched mode power supply.
2. Description of Related Art
Switched mode power supplies are known in the art to convert an available direct current (DC) or alternating current (AC) level voltage to another DC level voltage. A buck converter in one particular type of switched mode power supply that provides a regulated DC output voltage to a load by selectively storing energy in an output inductor coupled to the load by switching the flow of current into the output inductor. It includes two power switches that are typically provided by MOSFET transistors. A filter capacitor coupled in parallel with the load reduces ripple of the output current. A pulse width modulation (PWM) control circuit is used to control the gating of the power switches in an alternating manner to control the flow of current in the output inductor. The PWM control circuit uses signals communicated via a feedback loop reflecting the output voltage and/or current level to adjust the duty cycle applied to the power switches in response to changing load conditions.
Conventional PWM control circuits are constructed using analog circuit components, such as operational amplifiers, comparators and passive components like resistors and capacitors for the feedback loop compensation, as well as a few digital circuit component blocks like logical gates and flip-flops. But, it is desirable to use entirely digital circuitry instead of the analog circuit components since digital circuitry takes up less physical space, draws less power, and allows the implementation of programmability features or adaptive control techniques. A conventional digital control circuit includes an analog-to-digital converter (ADC) that converts an error signal representing the difference between a signal to be controlled (e.g., output voltage (Vo)) and a reference into a digital signal having n bits. The digital error signal is provided to a digital controller having a transfer function G(z) and shapes the open loop gain to guarantee stability of the power supply feedback loop with enough phase margin. The digital output of the controller is provided to a digital phase width modulator (DPWM) that converts the output into a proportional pulse width signal that is used to control the power switches of the power supply.
In order to keep the complexity of the PWM control circuit low, it is desirable to hold the number of bits of the digital signal to a small number. At the same time, however, the number of bits of the digital signal needs to be sufficiently high to provide resolution good enough to secure precise control of the output value. Moreover, the ADC needs to be very fast to respond to changing load conditions. Current microprocessors exhibit supply current slew rates of up to 20 A/μs, and future microprocessors are expected to reach slew rates greater than 350 A/μs, thereby demanding extremely fast response by the power supply. The bit size of the digital signal also affects the complexity of the digital circuitry that implements the transfer function G(z). To further reduce circuit complexity, mathematical calculations are preferably done using integer representation of the numbers and an internal scaling factor can be defined to improve the calculation precision.
Nevertheless, there is a continuing need to further reduce the complexity of the digital circuit while providing high calculation precision. Thus, it would be advantageous to provide a system and method for digitally controlling a switched mode power supply that overcomes these and other drawbacks of the prior art. More specifically, it would be advantageous to provide a digital signal processor architecture optimized for controlling a switched mode power supply.